Many modern computer architectures include a branch predictor that, in the event of a branch instruction, predicts which branch will be taken and speculatively fetches and executes instructions without having to wait until the branch is resolved.
In current branch prediction schemes lower bits of a program counter (PC) are used to index branch prediction entries stored in a branch prediction table. This means that if multiple branches have the same lower address, they will share the same branch prediction entry. This may be referred to as aliasing.
In a multi-threaded system, aliasing may be more prevalent due to multiple threads sharing the same branch predictor. This may easily happen if, for example, two threads are sharing the same code section.
In order to prevent this, one method may be to use a thread tag, which identifies the thread associated with an instruction, as one of the index bits for the branch history table. One drawback of this method, however, is the cost of such an approach: each thread now has an equally sized branch prediction table, with no regard to the bandwidth requirement of each thread and/or the code size of the thread.